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The ATA_GetDevConfig function allows an application to determine what the configuration is for a specified socket.
Some of the fields in this structure are changed or are not valid for ATA Manager 4.0 and later. See the field descriptions section for additional details.
The manager function code for the ATA_GetDevConfig function is $8A.
The parameter block associated with this function is defined as follows:
typedef | struct | ||
{ | |||
ataPBHdr | /* ataPBHdr parameter block */ | ||
SInt32 | ConfigSetting; | /* <--> 32 bits of */ /* configuration information */ |
|
UInt8 | ataPIOSpeedMode; | /* <-- Default PIO mode setting*/ | |
UInt8 | Reserved3; | /* Reserved for word alignment*/ | |
UInt16 | pcValid; | /* <-- PCMCIA unique */ | |
UInt16 | RWMultipleCount; | /* Reserved */ | |
UInt16 | SectorsPerCylinder; | /* Reserved */ | |
UInt16 | Heads; | /* Reserved */ | |
UInt16 | SectorsPerTrack; | /* Reserved */ | |
UInt16 | socketNum; | /* <-- Socket number */ | |
UInt8 | socketType; | /* <-- Type of socket */ | |
UInt8 | deviceType; | /* <-- Type of active device */ | |
UInt8 | pcAccessMode; | /* <-- Access mode of socket */ | |
UInt8 | pcVcc; | /* <-- device voltage */ | |
UInt8 | pcVpp1; | /* <-- Vpp 1 voltage */ | |
UInt8 | pcVpp2; | /* <-- Vpp 2 voltage */ | |
UInt8 | pcStatus; | /* <-- Status register setting */ | |
UInt8 | pcPin; | /* <-- Pin register setting */ | |
UInt8 | pcCopy; | /* <-- Copy register setting */ | |
UInt8 | pcConfigIndex; | /* <-- Option register setting */ | |
UInt8 | ataSingleDMASpeed; | /* <-- Single word DMA */ /* timing class */ |
|
UInt8 | ataMultiDMASpeed; | /* <-- Default Multiword DMA */ /* timing class */ |
|
UInt16 | ataPIOCycleTime; | /* <-- Default cycle time for */ /* PIO mode */ |
|
UInt16 | ataMultiCycleTime; | /* <-- Default cycle time for */ /* multiword DMA mode */ |
|
UInt16 | Reserved[7]; | /* Reserved*/ | |
} ataGetDevConfig; |
Bits 0-5: | Reserved, should be 0 |
Bit 6: | ATAPI packet DRQ handling setting.
0 = Check for assertion of cammand packet DRQ, this is the default setting. 1 = Check for interrupt DRQ command DRQ. |
Bits 7-31: | Reserved, must be 0 |
See Table A-1 for possible result codes returned by the ATA Manager.
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